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© 2025 Maktab-e-Digital Systems Lahore
Licensed under the Apache 2.0 License.
Overview
The JPEG Encoder project converts raw RGB images into JPEG compressed format using a hardware-based encoder implemented in SystemVerilog.
It is designed for real-time, low-power applications in embedded systems.
Compression Example
Before Compression vs After Compression
Workflow Flowchart
Overall flow of JPEG Compression Steps
Why JPEG?
Reduces file size by discarding perceptually insignificant data
Enables fast transmission and efficient memory use
Maintains high visual fidelity
Universally supported across hardware/software platforms
Repository Structure
The project is organized into RTL design, Testbenches, and SDK utilities.
Folder |
Description |
|---|---|
rtl/ |
Core SystemVerilog modules for JPEG encoder: |
testbenches/ |
Verification modules & input/output test data: |
sdk/ |
Scripts & tools for I/O and post-processing: |
Licensing
Licensed under the Apache License 2.0 Copyright © 2025 Maktab-e-Digital Systems Lahore