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© 2025 Maktab-e-Digital Systems Lahore
Licensed under the Apache 2.0 License.

Overview

The JPEG Encoder project converts raw RGB images into JPEG compressed format using a hardware-based encoder implemented in SystemVerilog.
It is designed for real-time, low-power applications in embedded systems.


Compression Example

Before Compression vs After Compression

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Workflow Flowchart

Flowchart

Overall flow of JPEG Compression Steps


Why JPEG?

  • Reduces file size by discarding perceptually insignificant data

  • Enables fast transmission and efficient memory use

  • Maintains high visual fidelity

  • Universally supported across hardware/software platforms


Repository Structure

The project is organized into RTL design, Testbenches, and SDK utilities.

Folder

Description

rtl/

Core SystemVerilog modules for JPEG encoder:
Color Conversion: rgb2ycbcr
DCT: y_dct, cb_dct, cr_dct (+ _constants.svh)
Quantizers: y_quantizer, cr_quantizer, cb_quantizer (+ _constants.svh)
Huffman: y_huff, cb_huff, cr_huff
Bitstream Handling: pre_fifo, sync_fifo_ff, sync_fifo_32, ff_checker, fifo_out
Combined: y_d_q_h, cb_d_q_h, cr_d_q_h

testbenches/

Verification modules & input/output test data:
rgb2ycbcr_tb/
dct_tb/
quantization_tb/
huffman_tb/
jpeg_top_TB/ – full encoder verification

sdk/

Scripts & tools for I/O and post-processing:
testimages/ – raw input images
output_images/ – compressed results
scripts/data_in.py – converts images to 24-bit BGR pixel data (pixel_data.txt)
raw_jpeg_bitstream_to_image/jpeg.py – merges headers + bitstreams into valid JPEG
Headers/ – predefined JPEG headers (.bin)
bitstream/ – sample bitstreams (.hex)
docs/ – diagrams & documentation

Licensing

Licensed under the Apache License 2.0 Copyright © 2025 Maktab-e-Digital Systems Lahore